In a design flow for an integrated circuit (IC) chip, after a gate-level netlist is partitioned into blocks, a top-level clock network is planned based on locations of the blocks. The top-level clock network includes clock trunks rooted from a clock source such as a phase-locked loop (PLL) and tapping points to which clock sinks such as registers are to be connected to. Then, cells that implement logic gates and registers in the gate-level netlist, respectively, are placed at specific locations in the IC chip design. Then, by creating clusters of registers associated to different tapping points, a clock network topology is generated. Then, clock network synthesis during which interconnections of the registers to the tapping points are routed is performed.
Like reference symbols in the various drawings indicate like elements.